Datasheet

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 486 of 910
REJ09B0350-0300
16.3.14 SCIF Control Register (SCIFCR)
SCIFCR controls SCIF operations, and is accessible only from the CPU.
Bit Bit Name Initial Value R/W Description
7
6
SCIFOE1
SCIFOE0
0
0
R/W
R/W
These bits enable or disable PORT output of the
SCIF.
For details, see table 16.5.
5 ⎯ 0 R/W Reserved
Do not change the initial value.
4 OUT2LOOP 0 R/W Enables or disables interrupts during a loopback
test.
0: Interrupt enabled
1: Interrupt disabled
3
2
CKSEL1
CKSEL0
0
0
R/W
R/W
These bits select the clock (SCLK) to be input to the
baud rate generator.
00: LCLK divided by 18
01: System clock divided by 11
10: Reserved for LCLK (not selectable)
11: Reserved for system clock (not selectable)
1 SCIFRST 0 R/W Resets the baud rate generator, FRSR, and FTSR.
0: Normal operation
1: Reset
0 REGRST 0 R/W Resets registers (except SCIFCR) accessible from
the H8S CPU or LPC interface.
0: Normal operation
1: Reset