Datasheet

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 484 of 910
REJ09B0350-0300
16.3.12 Modem Status Register (FMSR)
FMSR is a read-only register that indicates the status of or a change in the modem control pins.
Bit Bit Name Initial Value R/W Description
7 DCD Undefined R Data Carrier Detect
Indicates the inverted state of the DCD input pin.
6 RI Undefined R Ring Indicator
Indicates the inverted state of the RI input pin.
5 DSR Undefined R Data Set Ready
Indicates the inverted state of the DSR input pin.
4 CTS Undefined R Clear to Send
Indicates the inverted state of the CTS input pin.
3 DDCD 0 R Delta Data Carrier Indicator
Indicates a change in the DCD input signal after the
DDCD bit is read.
0: No change in the DCD input signal after FMSR
read
[Clearing condition]
FMSR read
1: A change in the DCD input signal after FMSR
read
[Setting condition]
A change in the DCD input signal
2 TERI 0 R Trailing Edge Ring Indicator
Indicates a rise in the RI input signal after the TERI
bit is read.
0: No change in the RI input signal after FMSR read
[Clearing condition]
FMSR read
1: A rise in the RI input signal after FMSR read
[Setting condition]
A rise in the RI input pin