Datasheet

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 477 of 910
REJ09B0350-0300
16.3.9 Line Control Register (FLCR)
FLCR sets formats of the transmit/receive data.
Bit Bit Name Initial Value R/W Description
7 DLAB 0 R/W Divisor Latch Address
FDLL and FDLH are placed at the same addresses
as the FRBR/FTHR and FIER addresses. This bit
selects which register is to be accessed.
0: FRBR/FTHR and FIER access enabled
1: FDLL and FDLH access enabled
6 BREAK 0 R/W Break Control
Generates a break by driving the serial output signal
FTxD low.
The break state is released by clearing this bit.
0: Break released
1: Break generated
5 STICK
PARITY
0 R Stick Parity
These bits are not supported in this LSI.
These bits are always read as 0 and cannot be
modified.
4 EPS 0 R/W Parity Select
Selects even or odd parity when the PEN bit is 1.
0: Odd parity
1: Even parity
3 PEN 0 R/W Parity Enable
Selects whether to add a parity bit for data
transmission and whether to perform a parity check
for data reception.
0: No parity bit added/parity check disabled
1: Parity bit added/parity check enabled