Datasheet

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 476 of 910
REJ09B0350-0300
16.3.8 FIFO Control Register (FFCR)
FFCR is a write-only register that controls transmit/receive FIFOs.
Bit Bit Name Initial Value R/W Description
7
6
RCVRTRIG1
RCVRTRIG0
0
0
W
W
Receive FIFO Interrupt Trigger Level 1, 0
These bits set the trigger level of the receive FIFO
interrupt.
00: 1 byte
01: 4 bytes
10: 8 bytes
11: 14 bytes
5, 4 – ⎯ ⎯ Reserved
These bits cannot be modified.
3 DMAMODE 0 ⎯ DMA Mode
This bit is not supported and cannot be modified.
2 XMITFRST 0 W Transmit FIFO Reset
The transmit FIFO data is cleared when 1 is written.
However, FTSR data is not cleared. This bit is
automatically cleared.
1 RCVRFRST 0 W Receive FIFO Reset
The receive FIFO data is cleared when 1 is written.
However, FRSR data is not cleared.
This bit is automatically cleared.
0 FIFOE 0 W FIFO Enable
0: Transmit/receive FIFOs disabled
All bytes of these FIFOs are cleared.
1: Transmit/receive FIFOs enabled