Datasheet

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 473 of 910
REJ09B0350-0300
• FDLL
Bit Bit Name Initial Value R/W Description
7 to 0 Bit 7 to
bit 0
All 0 R/W Lower 8 bits of divisor latch
Baud rate = (Clock frequency input to baud rate generator) / (16 × divisor value)
16.3.6 Interrupt Enable Register (FIER)
FIER is a register that enables or disables interrupts. It is accessible when the DLAB bit in FLCR
is 0.
Bit Bit Name Initial Value R/W Description
7 to 4 ⎯ All 0 R Reserved
This bit is always read as 0 and cannot be modified.
3 EDSSI 0 R/W Modem Status Interrupt Enable
0: Modem status interrupt disabled
1: Modem status interrupt enabled
2 ELSI 0 R/W Receive Line Status Interrupt Enable
0: Receive line status interrupt disabled
1: Receive line status interrupt enabled
1 ETBEI 0 R/W FTHR Empty Interrupt Enable
0: FTHR empty interrupt disabled
1: FTHR empty interrupt enabled
0 ERBFI 0 R/W Receive Data Ready Interrupt Enable
A character timeout interrupt is included when the
FIFO is enabled.
0: Receive data ready interrupt disabled
1: Receive data ready interrupt enabled