Datasheet

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 468 of 910
REJ09B0350-0300
Figure 16.1 shows a block diagram of the SCIF.
LPC
interface
Internal data bus
Bus interface
Modem
controller
PB2/RI
PB3/DCD
PB4/DSR
PB5/DTR
PB6/CTS
PB7/RTS
P50/FTxD
P51/FRxD
FRSR
FTSR
FTHR
FRBR
Transmit FIFO
(16 bytes)
Transmission
(1 byte)
Clock
selection/
divider
circuit
SCLK
FDLH
FDLL
Baud rate
generator
Transfer clock
SCIFCR
FIER
FIIR
FFCR
FLCR
FMCR
FLSR
FMSR
FSCR
Register
transmission/
reception
control
SCIF
interrupt
request
System clock
LCLK
Receive FIFO
(16 bytes)
Reception
(1 byte)
[Legend]
FRSR: Receive shift register
FTSR: Transmitter shift register
FRBR: Receive buffer register
FTHR: Transmitter holding register
FDLH, FDLL: Divisor latch H, L
FIER: Interrupt enable register
FIIR: Interrupt identification register
FFCR: FIFO control register
FLCR: Line control register
FMCR: Modem control register
FLSR: Line status register
FMSR: Modem status register
FSCR: Scratch pad register
SCIFCR: SCIF control register
Figure 16.1 Block Diagram of SCIF