Datasheet

Section 15 Serial Communication Interface (SCI)
Rev. 3.00 Sep. 28, 2009 Page 451 of 910
REJ09B0350-0300
15.7.4 Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the internal baud rate generator can be used as a
communication clock in smart card interface mode. In this mode, the SCI can operate using a
basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and
BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At
reception, the falling edge of the start bit is sampled using the internal basic clock in order to
perform internal synchronization. Receive data is sampled at the 16th, 32nd, 186th and 128th
rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in
figure 15.25. The reception margin here is determined by the following formula.
M = ⏐ (0.5 – ) – (L – 0.5) F – (1 + F) ⏐ × 100 [%]
...
Formula (1)
2N
1
N
⏐
D – 0.5
⏐
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock rate deviation
Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is
determined by the formula below.
M = (0.5 – 1 / 2 × 372) × 100 [%] = 49.866%
Internal
basic clock
372 clock cycles
186 clock
cycles
Receive data
(RxD)
Synchronization
sampling timing
D0 D1
Data sampling
timing
185 371 0371185 0
0
Start bit
Figure 15.25 Receive Data Sampling Timing in Smart Card Interface Mode
(When Clock Frequency is 372 Times the Bit Rate)