Datasheet

Section 15 Serial Communication Interface (SCI)
Rev. 3.00 Sep. 28, 2009 Page 402 of 910
REJ09B0350-0300
Clocked Synchronous Mode:
• Data length: 8 bits
• Receive error detection: Overrun errors
Smart Card Interface:
• An error signal can be automatically transmitted on detection of a parity error during reception.
• Data can be automatically re-transmitted on detection of an error signal during transmission.
• Both direct convention and inverse convention are supported.
Figure 15.1 shows a block diagram of SCI.
RxD
TxD
SCK
Clock
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
SCMR
SSR
SCR
SMR
Transmission/
reception control
Baud rate
generator
BRR
Module data bus
RDR
TSRRSR
Parity generation
Parity check
[Legend]
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
TDR
Bus interface
Internal data bus
External clock
SCR: Serial control register
SSR: Serial status register
SCMR: Smart card mode register
BRR: Bit rate register
Figure 15.1 Block Diagram of SCI