Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 3.00 Sep. 28, 2009 Page 399 of 910
REJ09B0350-0300
<TCNT write>
<TCSR write>
Address : H'FFA8
Address : H'FFA8
H'5A Write data
15 8 7 0
H'A5 Write data
15 8 7 0
Figure 14.5 Writing to TCNT and TCSR (WDT_0)
(2) Reading from TCNT and TCSR (Example of WDT_0)
These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR
and H'FFA9 for TCNT.
14.6.2 Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 14.6 shows this operation.
Address
φ
Internal write signal
TCNT input clock
TCNT
N
M
T
1
T
2
TCNT write cycle
Counter write data
Figure 14.6 Conflict between TCNT Write and Increment