Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 3.00 Sep. 28, 2009 Page 391 of 910
REJ09B0350-0300
14.2 Input/Output Pins
The WDT has the pins listed in table 14.1.
Table 14.1 Pin Configuration
Name Pin Name I/O Function
External sub-clock input pin EXCL Input Inputs the clock pulses to the WDT_1
prescaler counter
14.3 Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have
to be written to in a method different from normal registers. For details, see section 14.6.1, Notes
on Register Access. For details on the system control register, see section 3.2.2, System Control
Register (SYSCR).
Table 14.2 Register Configuration
Channel Register Name Abbreviation R/W Initial Value Address
Data Bus
Width
Timer counter_0 TCNT_0 R/W H'00 H'FFA8
H'FFA9*
16
8
Channel 0
Timer control/status
register_0
TCSR_0 R/W H'00 H'FFA8
H'FFA8*
16
8
Channel 1 Timer counter_1 TCNT_1 R/W H'00 H'FFEA
H'FFEB*
16
8
Timer control/status
register_1
TCSR_1 R/W H'00 H'FFEA
H'FFEA*
16
8
Note: * Address in the upper cell: when writing.
Address in the lower cell: when reading
14.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter.
TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared to
0.