Datasheet

Section 13 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 388 of 910
REJ09B0350-0300
13.9.6 Mode Setting with Cascaded Connection
If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock
pulses for TCNT_0 and TCNT_1, and TCNT_X and TCNT_Y are not generated, and thus the
counters will stop operating. Simultaneous setting of these two modes should therefore be
avoided.
13.9.7 Module Stop Mode Setting
TMR operation can be enabled or disabled using the module stop control register. The initial
setting is for TMR operation to be halted. Register access is enabled by canceling the module stop
mode. For details, see section 24, Power-Down Modes.