Datasheet

Section 13 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 365 of 910
REJ09B0350-0300
TCR TCRXY
Channel
CKS2 CKS1 CKS0 CKSX CKSY
Description
0 0 0 0 — Disables clock input
0 0 1 0 — Increments at φ
0 1 0 0 — Increments at φ/2
0 1 1 0 — Increments at φ/4
1 0 0 0 — Disables clock input
0 0 0 1 — Disables clock input
0 0 1 1 — Increments at φ/2048
0 1 0 1 — Increments at φ/4096
0 1 1 1 — Increments at φ/8192
1 0 0 1 — Increments at compare-match A from
TCNT_Y*
1 0 1 x — Increments at rising edge of external
clock
TMR_X
1 1 0 x — Increments at falling edge of external
clock
1 1 1 x — Increments at both rising and falling
edges of external clock
Note: * If the TMR_Y clock input is set as the TCNT_X overflow signal and the TMR_X clock
input is set as the TCNT_Y compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.
[Legend]
x: Don't care
⎯: Invalid