Datasheet

Section 13 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 364 of 910
REJ09B0350-0300
TCR STCR
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
1 0 1 — — Increments at rising edge of external
clock
Common
1 1 0 — — Increments at falling edge of external
clock
1 1 1 — — Increments at both rising and falling
edges of external clock
Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.
Table 13.3 Clock Input to TCNT and Count Condition (2)
TCR TCRXY
Channel CKS2 CKS1 CKS0 CKSX CKSY Description
0 0 0 — 0 Disables clock input
0 0 1 — 0 Increments at φ/4
0 1 0 — 0 Increments at φ/256
0 1 1 — 0 Increments at φ/2048
1 0 0 — 0 Disables clock input
0 0 0 — 1 Disables clock input
0 0 1 — 1 Increments at φ/4096
0 1 0 — 1 Increments at φ/8192
0 1 1 — 1 Increments at φ/16384
1 0 0 — 1 Increments at overflow signal from
TCNT_X*
1 0 1 — x Increments at rising edge of external
clock
TMR_Y
1 1 0 — x Increments at falling edge of external
clock
1 1 1 — x Increments at both rising and falling
edges of external clock