Datasheet

Section 13 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 363 of 910
REJ09B0350-0300
Table 13.3 Clock Input to TCNT and Count Condition (1)
TCR STCR
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0 0 0 — — Disables clock input
0 0 1 — 0 Increments at falling edge of internal
clock φ/8
0 0 1 — 1 Increments at falling edge of internal
clock φ/2
0 1 0 — 0 Increments at falling edge of internal
clock φ/64
0 1 0 — 1 Increments at falling edge of internal
clock φ/32
0 1 1 — 0 Increments at falling edge of internal
clock φ/1024
0 1 1 — 1 Increments at falling edge of internal
clock φ/256
TMR_0
1 0 0 — — Increments at overflow signal from
TCNT_1*
0 0 0 — — Disables clock input
0 0 1 0 — Increments at falling edge of internal
clock φ/8
0 0 1 1 — Increments at falling edge of internal
clock φ/2
0 1 0 0 — Increments at falling edge of internal
clock φ/64
0 1 0 1 — Increments at falling edge of internal
clock φ/128
0 1 1 0 — Increments at falling edge of internal
clock φ/1024
TMR_1
0 1 1 1 — Increments at falling edge of internal
clock φ/2048
1 0 0 — — Increments at compare-match A from
TCNT_0*