Datasheet

Section 13 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 360 of 910
REJ09B0350-0300
Channel Register Name Abbreviation R/W
Initial
Value
Address
Data
Bus
Width
Timer counter_X TCNT_X R/W H'00 H'FFF4 8
Time constant register A_X TCORA_X R/W H'FF H'FFF6 8
Time constant register B_X TCORB_X R/W H'FF H'FFF7 8
Timer control register_X TCR_X R/W H'00 H'FFF0 8
Timer control/status register_X TCSR_X R/W H'00 H'FFF1 8
Time constant register TCORC R/W H'FF H'FFF5 8
Input capture register R TICRR R H'00 H'FFF2 8
Input capture register F TICRF R H'00 H'FFF3 8
Channel X
Timer connection register I TCONRI R/W H'00 H'FFFC 8
Common Timer XY control register TCRXY R/W H'00 H'FEC6 8
Note: Some of the registers of TMR_X and TMR_Y use the same address. The registers can be
switched by the TMRX/Y bit in TCONRS.
TCNT_Y, TCORA_Y, TCORB_Y, and TCR_Y can be accessed when the RELOCATE bit in
SYSCR3 and the KINWUE bit in SYSCR are cleared to 0 and the TMRX/Y bit in TCONRS
is set to 1, or when the RELOCATE bit in SYSCR3 is set to 1. TCNT_X, TCORA_X,
TCORB_X, and TCR_X can be accessed when the RELOCATE bit in SYSCR3, the
KINWUE bit in SYSCR, and the TMRX/Y bit in TCONRS are cleared to 0, or when the
RELOCATE bit in SYSCR3 is set to 1.
13.3.1 Timer Counter (TCNT)
Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 (or TCNT_X and
TCNT_Y) comprise a single 16-bit register, so they can be accessed together by word access. The
clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external
reset input signal, compare-match A signal or compare-match B signal. The method of clearing
can be selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from
H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is initialized to H'00.