Datasheet

Section 13 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 359 of 910
REJ09B0350-0300
13.3 Register Descriptions
The TMR has the following registers. For details on the serial timer control register, see section
3.2.3, Serial Timer Control Register (STCR).
Table 13.2 Register Configuration
Channel Register Name Abbreviation R/W
Initial
Value
Address
Data
Bus
Width
Timer counter_0 TCNT_0 R/W H'00 H'FFD0 16
Time constant register A_0 TCORA_0 R/W H'FF H'FFCC 16
Time constant register B_0 TCORB_0 R/W H'FF H'FFCE 16
Timer control register_0 TCR_0 R/W H'00 H'FFC8 8
Channel 0
Timer control/status register_0 TCSR_0 R/W H'00 H'FFCA 8
Timer counter_1 TCNT_1 R/W H'00 H'FFD1 16
Time constant register A_1 TCORA_1 R/W H'FF H'FFCD 16
Time constant register B_1 TCORB_1 R/W H'FF H'FFCF 16
Timer control register_1 TCR_1 R/W H'00 H'FFC9 8
Channel 1
Timer control/status register_1 TCSR_1 R/W H'10 H'FFCB 8
Timer counter_Y TCNT_Y R/W H'00 H'FFF4
H'FECC*
8
Time constant register A_Y TCORA_Y R/W H'FF H'FFF2
H'FECA*
8
Time constant register B_Y TCORB_Y R/W H'FF H'FFF3
H'FECB*
8
Timer control register_Y TCR_Y R/W H'00 H'FFF0
H'FEC8*
8
Channel Y
Timer control/status register_Y TCSR_Y R/W H'00 H'FFF1
H'FEC9*
8
Timer connection register S TCONRS R/W H'00 H'FFFE 8
Note: * Upper address: when RELOCATE = 0
Lower address: when RELOCATE = 1