Datasheet

Section 12 16-Bit Duty Period Measurement Timer (TDP)
Rev. 3.00 Sep. 28, 2009 Page 339 of 910
REJ09B0350-0300
Bit Bit Name
Initial
Value
R/W Description
5 CPSPE 0 R/W Input Capture Stop Enable
Controls whether counting up by TDPCNT and input-
capture operation stop or continue when any of the
TPDMXOVF, TPDMNUDF, TWDMXOVF, and TWDMNUDF
flags is set to 1 in cycle measurement mode. This bit does
not affect operation in timer mode.
0: Counting up and input-capture operation continue when
any of the flags is set to 1.
1: Counting up and input-capture operation stop when any
of the flags is set to 1.
4 IEDG 0 R/W Input Edge Select
In timer mode, in combination with the value of the POCTL
bit, selects the falling or rising edge of the TDPCYI input for
capturing input.
In cycle measurement mode, this bit does not affect
operation.
When POCTL = 0
0: The falling edge of TDPCYI input is selected
1: The rising edge of TDPCYI input is selected
When POCTL = 1
0: The rising edge of TDPCYI input is selected
1: The falling edge of TDPCYI input is selected
3 TDPMDS 0 R/W TDP Mode Select
Selects the TDP operating mode.
0: Timer mode
In timer mode, the operating mode is input capture and
compare match.
1: Cycle measurement mode
Setting this bit to 1 starts counting by TDPCNT. Clear the
CST bit in TDPCR1 to initialize TDPCNT to H'0000
before setting cycle measurement mode.