Datasheet

Section 12 16-Bit Duty Period Measurement Timer (TDP)
Rev. 3.00 Sep. 28, 2009 Page 338 of 910
REJ09B0350-0300
Bit Bit Name
Initial
Value
R/W Description
0 TPDMNUDF 0 R/(W)* Cycle Lower Limit Underflow
This flag indicates that the waveform period measured in
cycle measurement mode is below the lower limit specified
in TDPPDMN.
[Setting condition]
• When TDPICR is less than TDPPDMN
[Clearing condition]
• Reading TPDMNUDF when TPDMNUDF = 1 and then
writing 0 to TPDMNUDF
Note: * Only 0 can be written to clear the flag.
12.3.9 TDP Control Register 1 (TDPCR1)
TDPCR1 selects the input capture input edge, starts the TDPCNT counter, selects the counter
clock, and controls the operating mode.
Bit Bit Name
Initial
Value
R/W Description
7 CST 0 R/W Counter Start
In timer mode, setting this bit to 1 starts counting by
TDPCNT, and clearing it stops counting. After the bit is
cleared, the counter is initialized to H'0000, and the input-
capture operation stops.
Clear this bit to initialize TDPCNT to H'0000 before setting
to cycle measurement mode.
6 POCTL 0 R/W TDPCYI Input Polarity Inversion
0: TDPCYI input is used directly
1: TDPCYI input is inverted for use
Note: Change this bit when CST = 0 and TDPMDS = 0.