Datasheet

Section 12 16-Bit Duty Period Measurement Timer (TDP)
Rev. 3.00 Sep. 28, 2009 Page 332 of 910
REJ09B0350-0300
12.3 Register Descriptions
The TDP has the following registers.
Table 12.2 Register Configuration
Channel Register Name Abbreviation R/W
Initial
Value
Address
Data
Bus
Width
TDP timer counter_0 TDPCNT_0 R/W H'0000 H'FB40 16
TDP pulse width upper limit register_0 TDPWDMX_0 R/W H'FFFF H'FB42 16
TDP pulse width lower limit register_0 TDPWDMN_0 R/W H'0000 H'FB44 16
TDP cycle upper limit register_0 TDPPDMX_0 R/W H'FFFF H'FB46 16
TDP cycle lower limit register_0 TDPPDMN_0 R/W H'0000 H'FB50 16
TDP input capture register_0 TDPICR_0 R H'0000 H'FB48 16
TDP input capture buffer register_0 TDPICRF_0 R H'0000 H'FB4A 16
TDP status register_0 TDPCSR_0 R/W H'00 H'FB4C 8
TDP control register1_0 TDPCR1_0 R/W H'00 H'FB4D 8
TDP control register2_0 TDPCR2_0 R/W H'00 H'FB4F 8
Channel 0
TDP interrupt enable register_0 TDPIER_0 R/W H'00 H'FB4E 8
TDP timer counter_1 TDPCNT_1 R/W H'0000 H'FB60 16
TDP pulse width upper limit register_1 TDPWDMX_1 R/W H'FFFF H'FB62 16
TDP pulse width lower limit register_1 TDPWDMN_1 R/W H'0000 H'FB64 16
TDP cycle upper limit register_1 TDPPDMX_1 R/W H'FFFF H'FB66 16
TDP cycle lower limit register_1 TDPPDMN_1 R/W H'0000 H'FB70 16
TDP input capture register_1 TDPICR_1 R H'0000 H'FB68 16
TDP input capture buffer register_1 TDPICRF_1 R H'0000 H'FB6A 16
TDP status register_1 TDPCSR_1 R/W H'00 H'FB6C 8
TDP control register1_1 TDPCR1_1 R/W H'00 H'FB6D 8
Channel 1
TDP control register2_1 TDPCR2_1 R/W H'00 H'FB6F 8
TDP interrupt enable register_1 TDPIER_1 R/W H'00 H'FB6E 8