Datasheet

Section 12 16-Bit Duty Period Measurement Timer (TDP)
Rev. 3.00 Sep. 28, 2009 Page 330 of 910
REJ09B0350-0300
Figure 12.1 shows a block diagram of the TDP.
Clock selection
TDPCSR
TDPICR
TDPCNT
TDPICRF
TDPCKI
External clock Internal clock
φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64
TDPMCI
TDPCYI
Control logic
Module data bus
TDPCR1
TDPCR2
TDPIER
TICI
TCMI
TWDMXI
TWDMNI
[Legend]
TDPCNT:
TDPPDMX:
TDPPDMN:
TDPWDMX:
TDPWDMN:
Timer counter
Cycle upper limit register
Cycle lower limit register
Pulse width upper limit register
Pulse width lower limit register
TDPICR:
TDPICRF:
TDPCSR:
TDPCR1:
TDPCR2:
TDPIER:
Input capture register
Input capture buffer register
Status register
Control register 1
Control register 2
Interrupt enable register
TPDMXI
TPDMNI
TOVI
TDPWDMX
Comparator
TDPWDMN
TDPPDMX
TDPPDMN
Input capture
Cycle upper limit overflow
Cycle lower limit underflow
Pulse width upper limit overflow
Pulse width lower limit underflow
Overflow
Clear
Compare match
Figure 12.1 Block Diagram of TDP