Datasheet

Section 11 16-Bit Cycle Measurement Timer (TCM)
Rev. 3.00 Sep. 28, 2009 Page 326 of 910
REJ09B0350-0300
11.6.3 Conflict between TCMICR Read and Input Capture
When operation is in timer mode and the corresponding input capture signal is detected during
reading of TCMICR, the input capture signal is delayed by one system clock (φ). Figure 11.15
shows the timing of this conflict.
φ
TCMCYI
TCMICR
read signal
TCMICR
ICPF
Input capture
signal
N + 2N + 1N Capture generatedN - 1
NM
TCMCNT
Figure 11.15 Conflict between TCMICR Read and Input Capture
11.6.4 Conflict between Edge Detection in Cycle Measurement Mode and Writing to
TCMMLCM or TCMMINCM
If the selected edge of TCMCYI is detected in the second half of a cycle of writing to the register
(TCMMLCM or TCMMINCM) in cycle measurement mode, the detected edge signal is delayed
by one cycle of the system clock (φ).
Figure 11.16 shows the timing of this conflict.
TCMICR > TCMCNT (Upper liit over)
Capture generated
φ
TCMCYI
Internal write
signal
TCMICR
MAXOVF
Input capture
signal
NM
H'0000N
TCMCNT
Figure 11.16 Conflict between Edge Detection and Register Write
(Cycle Measurement Mode)