Datasheet

Section 11 16-Bit Cycle Measurement Timer (TCM)
Rev. 3.00 Sep. 28, 2009 Page 325 of 910
REJ09B0350-0300
11.6 Usage Notes
11.6.1 Conflict between TCMCNT Write and Count-Up Operation
When a conflict between TCMCNT write and count-up operation occurs in the second half of the
TCMCNT write cycle, TCMCNT is not incremented and writing to TCMCNT takes priority.
Figure 11.13 shows the timing of this conflict.
φ
Internal write
signal
Internal clock
TCMCNT
input clock
T1
T2
TCMCNT N - 1 N N + 1
Figure 11.13 Conflict between TCMCNT Write and Count-Up Operation
11.6.2 Conflict between TCMMLCM Write and Compare Match
When a conflict between TCMMLCM write and a compare match should occur in the second half
of a cycle of writing to TCMMLCM, writing to TCMMLCM takes priority and the compare
match signal is inhibited. Figure 11.14 shows the timing of this conflict.
φ
Internal write
signal
TCMCNT
TCMMLCM
T1
T2
Compare match
signal
Inhibited
N N + 1
N + 2
N
M
Figure 11.14 Conflict between TCMMLCM Write and Compare Match