Datasheet

Section 11 16-Bit Cycle Measurement Timer (TCM)
Rev. 3.00 Sep. 28, 2009 Page 313 of 910
REJ09B0350-0300
11.3.7 TCM Control Register (TCMCR)
TCMCR is an 8-bit readable/writable register. TCMCR selects input capture input edge, counter
start, and counter clock, and controls operation mode.
Bit Bit Name
Initial
Value
R/W Description
7 CST 0 R/W Counter Start
In timer mode, setting this bit to 1 starts counting by
TCMCNT; clearing this bit stops counting by TCMCNT.
Then, the counter is initialized to H'0000, and input-capture
operation stops.
Clear this bit and thus return TCMCNT to H'0000 in
initialization for cycle measurement mode.
6 POCTL 0 R/W TCMCYI Input Polarity Reversal
0: Use the TCMCYI input directly
1: Use the inverted TCMCYI input
Note: Modify this bit while CST = 0 and TCMMDS = 0
5 CPSPE 0 R/W Input Capture Stop Enable
Controls whether or not counting up by TCMCNT and input-
capture operation stop or continue when either of MAXOVF
or MINUDF is set to 1 in cycle measurement mode. The bit
does not affect operation in timer mode.
0: Counting up and input-capture operation continue when
the flag is set to 1.
1: Counting up and input-capture operation are disabled
when the flag is set to 1.