Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep. 28, 2009 Page 301 of 910
REJ09B0350-0300
10.8.8 Conflict between TGR Write and Input Capture
If the input capture signal is generated in the T
2
state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed. Figure 10.49 shows the timing
in this case.
Input capture
signal
Write signal
Address
φ
TCNT
TGR write cycle
T1
T2
M
TGR
M
TGR address
Figure 10.49 Conflict between TGR Write and Input Capture
10.8.9 Conflict between Buffer Register Write and Input Capture
If the input capture signal is generated in the T
2
state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed. Figure 10.50
shows the timing in this case.