Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep. 28, 2009 Page 298 of 910
REJ09B0350-0300
10.8.3 Conflict between TCNT Write and Clear Operations
If the counter clear signal is generated in the T
2
state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed. Figure 10.44 shows the timing in this case.
Counter clear
signal
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1
T2
N H'0000
Figure 10.44 Conflict between TCNT Write and Clear Operations
10.8.4 Conflict between TCNT Write and Increment Operations
If incrementing occurs in the T
2
state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 10.45 shows the timing in this case.
TCNT input
clock
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1
T2
NM
TCNT write data
Figure 10.45 Conflict between TCNT Write and Increment Operations