Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep. 28, 2009 Page 297 of 910
REJ09B0350-0300
10.8 Usage Notes
10.8.1 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width. In phase counting mode, the phase difference and overlap between the two
input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure
10.43 shows the input clock conditions in phase counting mode.
Overlap
Phase
differ-
ence
Phase
differ-
enceOverlap
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width Pulse width
Pulse width Pulse width
Notes: Phase difference and overlap
Pulse width
: 1.5 states or more
: 2.5 states or more
Figure 10.43 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
10.8.2 Caution on Period Setting
When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
φ
f = ————
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set value