Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxxii of xliv
REJ09B0350-0300
Section 7 I/O Ports...........................................................................................135
7.1 Register Descriptions......................................................................................................... 143
7.1.1 Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to J) ............... 144
7.1.2 Data Register (PnDR) (n = 1 to 6, 8, and 9).......................................................... 145
7.1.3 Input Data Register (PnPIN) (n = 1 to 9 and A to J)............................................. 145
7.1.4 Pull-Up MOS Control Register (PnPCR) (n = 1 to 3, 9, B to D, F, H, and J)
Pull-Up MOS Control Register (KMPCR) (Port 6).............................................. 146
7.1.5 Output Data Register (PnODR) (n = A to D and F to J) ....................................... 149
7.1.6 Noise Canceller Enable Register (PnNCE) (n = 6, C, and G)............................... 149
7.1.7 Noise Canceller Decision Control Register (PnNCMC) (n = 6, C, and G)........... 150
7.1.8 Noise Cancel Cycle Setting Register (PnNCCS) (n = 6, C, and G) ...................... 150
7.1.9 Port Nch-OD Control Register (PnNOCR) (n = C, D, and F to J)........................ 152
7.1.10 Pin Functions ........................................................................................................ 153
7.2 Output Buffer Control........................................................................................................ 154
7.2.1 Port 1..................................................................................................................... 154
7.2.2 Port 2..................................................................................................................... 154
7.2.3 Port 3..................................................................................................................... 155
7.2.4 Port 4..................................................................................................................... 155
7.2.5 Port 5..................................................................................................................... 159
7.2.6 Port 6..................................................................................................................... 161
7.2.7 Port 7..................................................................................................................... 162
7.2.8 Port 8..................................................................................................................... 163
7.2.9 Port 9..................................................................................................................... 166
7.2.10 Port A.................................................................................................................... 168
7.2.11 Port B.................................................................................................................... 168
7.2.12 Port C.................................................................................................................... 172
7.2.13 Port D.................................................................................................................... 176
7.2.14 Port E .................................................................................................................... 176
7.2.15 Port F .................................................................................................................... 177
7.2.16 Port G.................................................................................................................... 180
7.2.17 Port H.................................................................................................................... 184
7.2.18 Port I ..................................................................................................................... 185
7.2.19 Port J ..................................................................................................................... 186
7.3 Change of Peripheral Function Pins................................................................................... 193
7.3.1 Port Control Register 0 (PTCNT0)....................................................................... 193
7.3.2 Port Control Register 1 (PTCNT1)....................................................................... 194
7.3.3 Port Control Register 2 (PTCNT2)....................................................................... 195