Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep. 28, 2009 Page 280 of 910
REJ09B0350-0300
Table 10.19 PWM Output Registers and Output Pins
Output Pins
Channel Registers PWM Mode 1 PWM Mode 2
TGRA_0 TIOCA0
TGRB_0
TIOCA0
TIOCB0
TGRC_0 TIOCC0
0
TGRD_0
TIOCC0
TIOCD0
TGRA_1 TIOCA1 1
TGRB_1
TIOCA1
TIOCB1
2 TGRA_2 TIOCA2 TIOCA2
TGRB_2 TIOCB2
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
(1) Example of PWM Mode Setting Procedure
Figure 10.21 shows an example of the PWM mode setting procedure.
PWM mode
Select counter clock
Select counter clearing source
Select waveform output level
Set TGR
Set PWM mode
Start count
<PWM mode>
Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0
in TCR.
Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
Set the cycle in the TGR selected in [2], and set
the duty in the other the TGR.
Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set the CST bit in TSTR to 1 start the count
operation.
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Figure 10.21 Example of PWM Mode Setting Procedure