Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxx of xliv
REJ09B0350-0300
2.7.3 Register Indirect with Displacement⎯@(d:16, ERn) or @(d:32, ERn)................. 58
2.7.4 Register Indirect with Post-Increment or Pre-Decrement⎯@ERn+ or @-ERn..... 58
2.7.5 Absolute Address⎯@aa:8, @aa:16, @aa:24, or @aa:32....................................... 58
2.7.6 Immediate⎯#xx:8, #xx:16, or #xx:32.................................................................... 59
2.7.7 Program-Counter Relative⎯@(d:8, PC) or @(d:16, PC)....................................... 59
2.7.8 Memory Indirect⎯@@aa:8 ................................................................................... 60
2.7.9 Effective Address Calculation ................................................................................ 61
2.8 Processing States.................................................................................................................. 63
2.9 Usage Note........................................................................................................................... 65
2.9.1 Notes on Using the Bit Operation Instruction......................................................... 65
Section 3 MCU Operating Modes .....................................................................67
3.1 Operating Mode Selection ................................................................................................... 67
3.2 Register Descriptions...........................................................................................................68
3.2.1 Mode Control Register (MDCR) ............................................................................ 68
3.2.2 System Control Register (SYSCR)......................................................................... 69
3.2.3 Serial Timer Control Register (STCR) ................................................................... 71
3.2.4 System Control Register 3 (SYSCR3).................................................................... 73
3.3 Operating Mode Descriptions.............................................................................................. 73
3.3.1 Mode 2.................................................................................................................... 73
3.4 Address Map........................................................................................................................ 74
Section 4 Exception Handling ........................................................................... 75
4.1 Exception Handling Types and Priority............................................................................... 75
4.2 Exception Sources and Exception Vector Table.................................................................. 76
4.3 Reset .................................................................................................................................... 79
4.3.1 Reset Exception Handling ...................................................................................... 79
4.3.2 Interrupts Immediately after Reset.......................................................................... 80
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled............................................ 80
4.4 Interrupt Exception Handling............................................................................................... 81
4.5 Trap Instruction Exception Handling................................................................................... 81
4.6 Exception Handling by Illegal Instruction ........................................................................... 82
4.7 Stack Status after Exception Handling................................................................................. 83
4.8 Usage Note........................................................................................................................... 84
Section 5 Interrupt Controller............................................................................85
5.1 Features................................................................................................................................ 85
5.2 Input/Output Pins................................................................................................................. 87
5.3 Register Descriptions...........................................................................................................88
5.3.1 Interrupt Control Registers A to D (ICRA to ICRD).............................................. 89