Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep. 28, 2009 Page 266 of 910
REJ09B0350-0300
H
L
TCR
Internal data bus
Bus interface
Module
data bus
Bus
master
Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
H
L
TMDR
Internal data bus
Bus interface
Module
data bus
Bus
master
Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
H
L
TCR TMDR
Internal data bus
Bus interface
Module
data bus
Bus
master
Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]