Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep. 28, 2009 Page 252 of 910
REJ09B0350-0300
Table 10.12 TIORL_0 (channel 0)
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_0
Function
TIOCD0 Pin Function
0 Output disabled 0
1 Initial output is 0 output
0 output at compare match
0 Initial output is 0 output
1 output at compare match
0
1
1 Initial output is 0 output
Toggle output at compare match
0 Output disabled 0
1 Initial output is 1 output
0 output at compare match
0 Initial output is 1 output
1 output at compare match
0
1
1
1
Output
Compare
register*
Initial output is 1 output
Toggle output at compare match
0 Capture input source is TIOCD0 pin
Input capture at rising edge
0
1 Capture input source is TIOCD0 pin
Input capture at falling edge
1 0
1 ×
Input capture
register*
Capture input source is TIOCD0 pin
Input capture at both edges
1 × × Setting prohibited
[Legend]
×: Don't care
Note: When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.