Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep. 28, 2009 Page 243 of 910
REJ09B0350-0300
Channel Register Name Abbreviation R/W
Initial
Value
Address
Data Bus
Width
Timer general register A_2 TGRA_2 R/W H'FFFF H'FE78 16
Channel 2
Timer general register B_2 TGRB_2 R/W H'FFFF H'FE7A 16
Common Timer start register TSTR R/W H'00 H'FEB0 8
Timer synchro register TSYR R/W H'00 H'FEB1 8
10.3.1 Timer Control Register (TCR)
The TCR registers control the TCNT operation for each channel. The TPU has a total of three
TCR registers, one for each channel (channel 0 to 2). TCR register settings should be made only
when TCNT operation is stopped.
Bit Bit Name
Initial
value
R/W Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 2 to 0
These bits select the TCNT counter clearing source.
See tables 10.4 and 10.5 for details.
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock cycle
is divided in 2 (φ/4 both edges = φ/2 rising edge). If
phase counting mode is used on channels 1, 2, 4, and
5, this setting is ignored and the phase counting mode
setting has priority. Internal clock edge selection is valid
when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1 and rising edge count is
selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 10.6 to 10.8 for details.
[Legend]
x: Don't care