Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep. 28, 2009 Page 242 of 910
REJ09B0350-0300
10.3 Register Descriptions
The TPU has the following registers.
Table 10.3 Register Configuration
Channel Register Name Abbreviation R/W
Initial
Value
Address
Data Bus
Width
Timer control register_0 TCR_0 R/W H'00 H'FE50 8
Timer mode register_0 TMDR_0 R/W H'C0 H'FE51 8
Timer I/O control register H_0 TIORH_0 R/W H'00 H'FE52 8
Timer I/O control register L_0 TIORL_0 R/W H'00 H'FE53 8
Timer interrupt enable register_0 TIER_0 R/W H'40 H'FE54 8
Timer status register_0 TSR_0 R/W H'C0 H'FE55 8
Timer counter_0 TCNT_0 R/W H'0000 H'FE56 16
Timer general register A_0 TGRA_0 R/W H'FFFF H'FE58 16
Timer general register B_0 TGRB_0 R/W H'FFFF H'FE5A 16
Timer general register C_0 TGRC_0 R/W H'FFFF H'FE5C 16
Channel 0
Timer general register D_0 TGRD_0 R/W H'FFFF H'FE5E 16
Timer control register_1 TCR_1 R/W H'00 H'FD40 8
Timer mode register_1 TMDR_1 R/W H'C0 H'FD41 8
Timer I/O control register _1 TIOR_1 R/W H'00 H'FD42 8
Timer interrupt enable register_1 TIER_1 R/W H'40 H'FD44 8
Timer status register_1 TSR_1 R/W H'C0 H'FD45 8
Timer counter_1 TCNT_1 R/W H'0000 H'FD46 16
Timer general register A_1 TGRA_1 R/W H'FFFF H'FD48 16
Channel 1
Timer general register B_1 TGRB_1 R/W H'FFFF H'FD4A 16
Timer control register_2 TCR_2 R/W H'00 H'FE70 8
Timer mode register_2 TMDR_2 R/W H'C0 H'FE71 8
Timer I/O control register_2 TIOR_2 R/W H'00 H'FE72 8
Timer interrupt enable register_2 TIER_2 R/W H'40 H'FE74 8
Channel 2
Timer status register_2 TSR_2 R/W H'C0 H'FE75 8
Timer counter_2 TCNT_2 R/W H'0000 H'FE76 16