Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep. 28, 2009 Page 238 of 910
REJ09B0350-0300
Channel 2
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
TGRC
Channel 1
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
Channel 0
Control logic for channel 0 to 2
TGRA
TCNT
TGRB
TGRD
Bus
interface
Common
TSYR
Control logic
TSTR
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
TCLKA
TCLKB
TCLKC
TCLKD
[Legend]
TSTR:
TSYR:
TCR:
TMDR:
Timer start register
Timer synchro register
Timer control register
Timer mode register
Timer I/O control registers (H, L)
Timer interrupt enable register
Timer status register
TImer general registers (A, B, C, D)
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
Interrupt request signals
Channel 0:
Channel 1:
Channel 2:
Internal data bus
A/D converter convertion
start signal
Module data bus
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
TMDR
TSR
TCR
TIORH
TIER
TIORL
Input/output pins
Channel 0:
Channel 1:
Channel 2:
Clock input
Internal clock:
External clock:
TIOR (H, L):
TIER:
TSR:
TGR (A, B, C, D):
Figure 10.1 Block Diagram of TPU