Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxvi of xliv
REJ09B0350-0300
Item Page Revision (See Manual for Details)
25.5 Register Addresses
(Classification by Type of Module)
873 Table amended
2
2
2
2
2
2
2
2
1H'FC00
H'FC02
H'FC04
H'FC06
H'FC08
H'FC0A
H'FC0C
H'FC0E
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Module Address
Register
Abbreviation
Number of
Bits
Data Bus
Width
Access
States
A/D
converter
A/D
converter
A/D
converter
A/D
converter
A/D
converter
A/D
converter
A/D
converter
A/D
converter
ADDRA
ADDRB
ADDRC
ADDRD
ADDRE
ADDRF
ADDRG
ADDRH
26.3.2 Control Signal Timing
Figure 26.8 Interrupt Input
Timing
885 Figure amended
t
IRQS
t
IRQH
KINi
(i = 0 to 15)
WUEi
(i = 8 to 15)
t
IRQW
26.3.3 Timing of On-Chip
Peripheral Modules
Table 26.8 PS2 Timing
890 Table amended
Remarks
Figure
26.22
Table 26.9 I
2
C Bus Timing 892 Table amended
Test
Conditions
Figure
26.23
Table 26.10 LPC Timing 893 Table amended
Test
Conditions
Figure
26.24