Datasheet

Section 9 14-Bit PWM Timer (PWMX)
Rev. 3.00 Sep. 28, 2009 Page 221 of 910
REJ09B0350-0300
9.3.1 PWMX (D/A) Counter (DACNT)
DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select
bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a
channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12-
bit precision, it uses the lower 12 bits and ignores the upper 2-bit counter. As DACNT is 16 bits,
data transfer between the CPU is performed through the temporary register (TEMP). For details,
see section 9.4, Bus Master Interface.
7 6 5 4 3 2 1 0 8 9 10 11 12 13
15
Bit (counter):
Bit (CPU): 14
DACNTH DACNTL
13 12 11 10 9 8 7 6 5 4 3 2 1
0
REGS
• DACNTH
Bit Bit Name
Initial
Value
R/W Description
7 to 0 DACNT7 to
DACNT0
All 0 R/W Upper Up-Counter
• DACNTL
Bit Bit Name
Initial
Value
R/W Description
7 to 2 DACNT 8 to
DACNT 13
All 0 R/W Lower Up-Counter
1 ⎯ 1 R Reserved
Always read as 1 and cannot be modified.
0 REGS 1 R/W Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies
which registers can be accessed.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed