Datasheet

Section 8 8-Bit PWM Timer (PWMU)
Rev. 3.00 Sep. 28, 2009 Page 212 of 910
REJ09B0350-0300
When the PWMnE bit (n = 0 to 5) in PWMCONB is set to 1, the PWMU outputs pulses that start
with a high level. The updated PWMREG value is written in REGLAT, and the updated
PWMPRE value is written in PRELAT.
When the REGLAT value is less than the duty counter value, the PWMU outputs a high level
(when direct output is selected). At each PWM clock timing, the duty counter is incremented.
When the clock generator counter is H'00, the PWM clock is generated by decrementing the
PRELAT value.
Figure 8.4 shows an example of duty counter and clock generator counter operation.
H'78
φ
φ/4
Duty
counter
Clock generator
counter
PRELAT
REGLAT
PWMUO
H'79 H'80
H'80
H'81
H'01 H'01
H'01
H'01 H'01H'00 H'00 H'00
H'00
Figure 8.4 Example of Duty Counter and Clock Generator Counter Operation
(When PWMPRE = H'01 and PWMREG = H'80 with φ/4 Selected as Count Clock Source)
The following shows the duty counter value and PWMU output timing.
H'FF
Duty counter
REGLAT
H'00
PWMUO
Figure 8.5 Duty Counter Value and PWMU Output Timing