Datasheet

Section 8 8-Bit PWM Timer (PWMU)
Rev. 3.00 Sep. 28, 2009 Page 207 of 910
REJ09B0350-0300
8.3.5 PWM Prescaler Registers 0 to 5 (PWMPRE0 to PWMPRE5)
PWMPRE are 8-bit readable/writable registers used to set the PWM cycle. The initial value is
H'00.
When the PWMPRE value is n, the PWM cycle is calculated as follows.
(1) 8-Bit Single Pulse Mode
PWM cycle = [255 × (n + 1)] / internal clock frequency (0 ≤ n ≤ 255)
Table 8.3 Resolution, PWM Conversion Period, and Carrier Frequency (8-Bit Counter
Operation) when φ = 20 MHz
Carrier Frequency
PWM Conversion Period Single Pulse Mode
Internal Clock
Frequency
Resolution Min. Max. Min. Max.
φ 50 ns 12.8 μs 3.3 ms 306.4 Hz 78.4 kHz
φ/2 100 ns 25.5 μs 6.5 ms 153.2 Hz 39.2 kHz
φ/4 200 ns 51.2 μs 13.1 ms 76.6 Hz 19.6 kHz
φ/8 400 ns 102 μs 26.1 ms 38.3 Hz 9.8 kHz