Datasheet

Section 8 8-Bit PWM Timer (PWMU)
Rev. 3.00 Sep. 28, 2009 Page 202 of 910
REJ09B0350-0300
8.3.1 PWM Control Register A (PWMCONA)
PWMCONA selects the PWM clock source.
Bit Bit Name
Initial
Value
R/W Description
7, 6 CLK1, CLK0 All 0 R/W Clock Select 1, 0
These bits select the PWM count clock source.
CLK1 CLK0
0 0: Internal clock φ is selected
0 1: Internal clock φ/2 is selected
1 0: Internal clock φ/4 is selected
1 1: Internal clock φ/8 is selected
5 to 0 – All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
8.3.2 PWM Control Register B (PWMCONB)
PWMCONB controls enabling and disabling of the PWM output and counter operation of each
channel.
Bit Bit Name
Initial
Value
R/W Description
7, 6 ⎯ All 0 R/W Reserved
The initial value should not be changed.
5 PWM5E 0 R/W PWMU5 Output Enable
0: PWMU5 output and counter operation are
disabled.
1: PWMU5 output and counter operation are
enabled.