Datasheet

Section 7 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 188 of 910
REJ09B0350-0300
Port
Output
Specification
Signal Name
Output
Signal
Name
Signal Selection
Register Settings
Internal Module Settings
PWX1_OE PWX1 PWMX.DACR.OEB = 1
7
PWMU5B_OE PWMU5B PWMU_B.PWMCONB.PWM5E = 1
PWX0_OE PWX0 PWMX.DACR.OEA = 1 6
PWMU4B_OE PWMU4B PWMU_B.PWMCONB.PWM4E = 1,
PWMU_B.PWMCOND.CNTMD45 = 0
5 PWMU3B_OE PWMU3B PWMU_B.PWMCONB.PWM3E = 1
TMO1_OE TMO1 Except TMR_1.TCSR.OS[3:0] = 0000 4
PWMU2B_OE PWMU2B PWMU_B.PWMCONB.PWM2E = 1,
PWMU_B.PWMCOND.CNTMD23 = 0
3 SCK2_OE SCK2 SCI_2.SCR.CKE[1:0] = 01/10/11 + SMR.C/A
= 1
2 SDA1_OE SDA1 PTCNT1.IIC1AS
PTCNT1.IIC1BS
ICE•IIC1AS•IIC1BS = 1
1 TMO0_OE TMO0 Except TMR_0.TCSR.OS[3:0] = 0000
P4
0 TxD2_OE TxD2 SCI_2.SCR.TE = 1
2 SCL0_OE SCL0 PTCNT1.IIC1AS
PTCNT1.IIC1BS
ICE•IIC0AS•IIC0BS = 1
1 P51_OE P51
P5
0 FTxD_OE FTxD SCIF.SCIFCR.SCIFOE1, LPC.HICR5.SCIFE
SCIFENABLE = 1: SCIFOE1 + SCIFE
7 P67_OE P67
6 P66_OE P66
5 P65_OE P65
4 P64_OE P64
3 P63_OE P63
2 P62_OE P62
P6
1 P61_OE P61
0 P60_OE P60