Datasheet

Section 7 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 174 of 910
REJ09B0350-0300
(5) PC3/WUE11/TIOCD0/TCLKB
The pin function is switched as shown below according to the combination of the register setting
of the TPU and the PC3DDR bit. When the WUEMR11 bit in WUEMR of the interrupt controller
is cleared to 0, this pin can be used as the WUE11 input pin.
This pin functions as TCLKB input when TPSC2 to TPSC0 in any of TCR_0 to TCR_2 are set to
B'101 or when channel 1 is set to phase counting mode.
This pin functions as TIOCD1 input when TPU channel 0 timer operating mode is set to normal
operation or phase counting mode and IOD3 to IOD0 in TIOR_0 are set to B'10xx. (x: Don't care.)
Setting
TPU I/O Port
Module
Name
Pin Function
TIOCD0_OE PC3DDR
TPU TIOCD0 output 1 ⎯
I/O port PC3 output 0 1
PC3 input
(initial setting)
0 0
(6) PC2/WUE10/TIOCC0/TCLKA
The pin function is switched as shown below according to the combination of the register setting
of the TPU and the PC2DDR bit. When the WUEMR10 bit in WUEMR of the interrupt controller
is cleared to 0, this pin can be used as the WUE10 input pin.
This pin functions as TCLKA input when TPSC2 to TPSC0 in any of TCR_0 to TCR_2 are set to
B'100 or when channel 1 is set to phase counting mode.
This pin functions as TIOCC0 input when TPU channel 0 timer operating mode is set to normal
operation or phase counting mode and IOC3 to IOC0 in TIOR_0 are set to B'10xx. (x: Don't care.)
Setting
TPU I/O Port
Module
Name
Pin Function
TIOCC0_OE PC2DDR
TPU TIOCC0 output 1 ⎯
I/O port PC2 output 0 1
PC2 input
(initial setting)
0 0