Datasheet

Section 7 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 168 of 910
REJ09B0350-0300
7.2.10 Port A
(1) PA7/KIN15 /PS2CD, PA6/KIN14/PS2CC, PA5/KIN13/PS2BD, PA4/KIN1 2 /PS2BC,
PA3/KIN11/PS2AD, PA2/KIN10/PS2AC, PA1/KIN9/PS2DD, PA0/KIN8/PS2DC
The pin function is switched according to the combination of the register setting of PS2 and the
PAnDDR bit. When the KMIMRm bit in KMIMRA of the interrupt controller is cleared to 0, this
pin can be used as the KINm input pin.
Setting
PS2 I/O Port
Module
Name
Pin Function
PS2_OE PAnDDR
PS2 PS2 input/output 1 ⎯
I/O port PAn output 0 1
PAn input
(initial setting)
0 0
(n = 7 to 0, m = 15 to 8)
Note: When the KBIOE bit is set to 1, this pin functions as an NMOS open-drain output, and direct
bus drive is possible.
When the IICS bit in STCR is set to 1, the output format for PA7 to PA4 is NMOS open-
drain, and direct bus drive is possible.
7.2.11 Port B
(1) PB7/RTS
The pin function is switched as shown below according to the combination of the SCIFE bit in
HICR5 of LPC and the PB7DDR bit.
Setting
SCIF I/O Port
Module
Name
Pin Function
RTS_OE PB7DDR
SCIF RTS output 1 ⎯
I/O port PB7 output 0 1
PB7 input
(initial setting)
0 0