Datasheet

Section 7 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 160 of 910
REJ09B0350-0300
(2) P51/FRxD
The pin function is switched as shown below according to the SCIFOE1 bit in SCIFCR of the
SCIF and the SCIFE bit in HICR5 of the SCIF, and the P51DDR bit.
SCIFENABLE = 1: SCIFOE1 + SCIFE
Setting
Logical Expression I/O Port
Module
Name
Pin Function
SCIFENABLE P51DDR
SCIF FRxD input 1 ⎯
I/O port P51 output 0 1
P51 input
(initial setting)
0 0
(3) P50/FTxD
The pin function is switched as shown below according to the SCIFOE1 bit in SCIFCR of the
SCIF, the SCIFE bit in HICR5, and the P50DDR bit.
SCIFENABLE = 1: SCIFOE1 + SCIFE
Setting
Logical Expression I/O Port
Module
Name
Pin Function
SCIFENABLE P50DDR
SCIF FTxD output 1 ⎯
I/O port P50 output 0 1
P50 input
(initial setting)
0 0