Datasheet

Section 7 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 155 of 910
REJ09B0350-0300
7.2.3 Port 3
(1) P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2,
P31/LAD1, P30/LAD0
The pin function is switched as shown below according to the combination of the SCIFE bit in
HICR5 and LPC4E bit in HICR4 and LPC3E to LPC1E bits in HICR0 of the LPC, and the
P3nDDR bit. LPCENABLE in the following table is expressed by the following logical
expression.
LPCENABLE = 1: SCIFE + LPC4E + LPC3E + LPC2E + LPC1E
Setting
Logical expression I/O Port
Module
Name
Pin Function
LPCENABLE P3nDDR
LPC LPC input/output 1 ⎯
I/O port P3n output 0 1
P3n input
(initial setting)
0 0
(n = 7 to 0)
7.2.4 Port 4
(1) P47/PWX1/PWMU5B/TCMCKI3/TCMMCI3
The pin function is switched as shown below according to the combination of the PWMX and
PWMU and the P47DDR bit.
Setting
PWMX PWMU I/O Port
Module
Name
Pin Function
PWX1_OE PWMU5B_OE P47DDR
PWMX PWX1 output 1 ⎯ ⎯
PWMU PWMU5B output 0 1 1
I/O port P47 output 0 0 1
P47 input
(initial setting)
0 ⎯ 0