Datasheet

Section 7 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 151 of 910
REJ09B0350-0300
Sampling
clock
Port data
register
Interrupt input
Keyboard input
Sampling clock selection
Latch
Pin
input
Latch
Latch
Matching detection circuit
Latch
φ/2, φ/32, φ/8192, φ/16384, φ/32768,
φ/65536, φ/131072, φ/262144
t
t
Figure 7.1 Noise Cancel Circuit
P6n input
PCn input
PGn input
(n = 7 to 0)
1 expected
P6n input
PCn input
PGn input
0 expected
P6n input
PCn input
PGn input
Figure 7.2 Schematic View of Noise Cancel Operation