Datasheet

Section 7 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 150 of 910
REJ09B0350-0300
7.1.7 Noise Canceller Decision Control Register (PnNCMC) (n = 6, C, and G)
NCMC controls whether 1 or 0 is expected for the input signal to port n pins in bit units.
Bit Bit Name Initial Value R/W Description
7 Pn7NCMC 0 R/W
6 Pn6NCMC 0 R/W
5 Pn5NCMC 0 R/W
4 Pn4NCMC 0 R/W
3 Pn3NCMC 0 R/W
2 Pn2NCMC 0 R/W
1 Pn1NCMC 0 R/W
1 expected: 1 is stored in the port data register
when 1 is input stably.
0 expected: 0 is stored in the port data register
when 0 is input stably.
0 Pn0NCMC 0 R/W
7.1.8 Noise Cancel Cycle Setting Register (PnNCCS) (n = 6, C, and G)
NCCS controls the sampling cycles of the noise canceller.
Bit Bit Name Initial Value R/W Description
7 to 3
⎯ Undefined R/W Reserved
The read value is undefined. The write value
should always be 0.
2 PnNCCK2 0 R/W
1 PnNCCK1 0 R/W
0 PnNCCK0 0 R/W
These bits set the sampling cycles of the noise
canceller.
When φ is 10 MHz
000: 0.80 μs φ/2
001: 12.8 μs φ/32
010: 3.3 ms φ/8192
011: 6.6 ms φ/16384
100: 13.1 ms φ/32768
101: 26.2 ms φ/65536
110: 52.4 ms φ/131072
111: 104.9 ms φ/262144