Datasheet

Section 7 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 144 of 910
REJ09B0350-0300
7.1.1 Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to J)
DDR specifies the port input or output for each bit.
The upper five bits in P5DDR, the upper one bit in P8DDR, and the upper two bits in PHDDR are
reserved.
(1) PORTS = 0
Bit Bit Name Initial Value R/W Description
7 Pn7DDR 0 W
6 Pn6DDR 0 W
5 Pn5DDR 0 W
4 Pn4DDR 0 W
3 Pn3DDR 0 W
2 Pn2DDR 0 W
1 Pn1DDR 0 W
The corresponding pins act as output ports when
these bits are set to 1 and act as input ports when
cleared to 0.
Note: These bits cannot be set with bit manipulation
instructions such as BSET and BCLR.
0 Pn0DDR 0 W
(2) PORTS = 1
Bit Bit Name Initial Value R/W Description
7 Pn7DDR 0 R/W
6 Pn6DDR 0 R/W
5 Pn5DDR 0 R/W
4 Pn4DDR 0 R/W
3 Pn3DDR 0 R/W
2 Pn2DDR 0 R/W
1 Pn1DDR 0 R/W
The corresponding pins act as output ports when
these bits are set to 1 and act as input ports when
cleared to 0.
0 Pn0DDR 0 R/W