Datasheet

Rev. 3.00 Sep. 28, 2009 Page xvi of xliv
REJ09B0350-0300
Item Page Revision (See Manual for Details)
18.5.4 Medium-Speed Mode 588 Description amended
In medium-speed mode, the PS2 operates with the
medium-speed clock. For normal operation of the PS2,
set the medium-speed clock to a frequency of 300 kHz
or higher.
19.3 Register Descriptions
Table 19.2 Register
Configuration
594 Table amended
Register Name Abbreviation Address
Initial
Value
Data Bus
Width
R/W
Slave Host
Bidirectional data register 0MW
Bidirectional data register 0SW
TWR0MW
TWR0SW
H'FE20
H'FE20
H'00
H'00
8
8
R
W
W
R
19.3.11 Bidirectional Data
Registers 0 to 15 (TWR0 to
TWR15)
613 Description amended
When the host and slave begin a write, after the
respective registers of TWR0 have been written to,
arbitration for simultaneous access is performed by
checking the status flags whether or not those writes
were valid.
When the host has access rights, TWR0MW is
selected in TWR0 and the state of TWR0MW is
returned when the host reads TWR0SW. Attempts by
the slave to write to TWR0SW are invalid.
When the slave has access rights, TWR0SW is
selected in TWR0 and the state of TWR0SW is
returned when the slave reads TWR0MW. Attempts by
the host to write to TWR0MW are invalid.
For the registers selected from the host according to
the I/O address, see section 19.3.7, LPC Channel 3
Address Registers H and L (LADR3H and LADR3L).
19.3.12 Status Registers 1 to 4
(STR1 to STR4)
• STR4
619 Table amended
Bit Bit Name Initial Value Slave Host Description
0 OBF4 0 R/(W)* R Output Buffer Full
0: [Clearing conditions]
• When the host reads ODR4 in I/O read cycle
• When the slave writes 0 to the OBF4 bit
1: [Setting condition]
When the slave writes to ODR4
R/W