Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 125 of 910
REJ09B0350-0300
5.6.4 Interrupt Response Times
Table 5.10 shows interrupt response times − the intervals between generation of an interrupt
request and execution of the first instruction in the interrupt handling routine.
Table 5.10 Interrupt Response Times
No. Execution Status Advanced Mode
1 Interrupt priority determination*
1
3
2 Number of wait states until executing instruction
ends*
2
1 to 21
3 Saving of PC and CCR in stack 2
4 Vector fetch 2
5 Instruction fetch*
3
2
6 Internal processing*
4
2
Total (using on-chip memory) 12 to 32
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and prefetch of interrupt handling routine.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.