Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 115 of 910
REJ09B0350-0300
Vector Address Origin of
Interrupt
Source Name
Vector
Number
Advanced Mode ICR Priority
TDP_2 TICI2 (Input capture)
TCMI2 (Compare match)
TPDMXI2 (Cycle overflow)
TPDMNI2 (Cycle underflow)
TWDMNI2 (Pulse width lower limit
underflow)
TWDMXI2 (Pulse width upper limit
overflow)
TOVI2 (Overflow)
54 H'0000D8 ICRB5
— Reserved for system use 55 H'0000DC —
High
External
pin
IRQ8
IRQ9
IRQ10
IRQ11
56
57
58
59
H'0000E0
H'0000E4
H'0000E8
H'0000EC
ICRD7
IRQ12
IRQ13
IRQ14
IRQ15
60
61
62
63
H'0000F0
H'0000F4
H'0000F8
H'0000FC
ICRD6
TMR_0 CMIA0 (Compare match A)
CMIB0 (Compare match B)
OVI0 (Overflow)
64
65
66
H'000100
H'000104
H'000108
ICRB3
— Reserved for system use 67 H'00010C —
TMR_1 CMIA1 (Compare match A)
CMIB1 (Compare match B)
OVI1 (Overflow)
68
69
70
H'000110
H'000114
H'000118
ICRB2
— Reserved for system use 71 H'00011C —
TMR_X
TMR_Y
CMIAY (Compare match A)
CMIBY (Compare match B)
OVIY (Overflow)
ICIX (Input capture)
CMIAX (Compare match A)
CMIBX (Compare match B)
OVIX (Overflow)
72
73
74
75
76
77
78
H'000120
H'000124
H'000128
H'00012C
H'000130
H'000134
H'000138
ICRB1
⎯
Reserved for system use 79
⏐
81
H'00013C
⏐
H'000144
—
SCIF SCIF (SCIF interrupt) 82 H'000148 ICRC7
⎯
Reserved for system use 83 H'00014C —
SCI_1 ERI1 (Reception error 1)
RXI1 (Reception completion 1)
TXI1 (Transmission data empty 1)
TEI1 (Transmission end 1)
84
85
86
87
H'000150
H'000154
H'000158
H'00015C
ICRC6
Low